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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 40
701702703704705706707708709710
FTMx_SYNC field descriptions (continued)
Field Description
0 Trigger is disabled.
1 Trigger is enabled.
5
TRIG1
PWM Synchronization Hardware Trigger 1
Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 happens when a rising edge
is detected at the trigger 1 input signal.
0 Trigger is disabled.
1 Trigger is enabled.
4
TRIG0
PWM Synchronization Hardware Trigger 0
Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0 happens when a rising edge
is detected at the trigger 0 input signal.
0 Trigger is disabled.
1 Trigger is enabled.
3
SYNCHOM
Output Mask Synchronization
Selects when the OUTMASK register is updated with the value of its buffer.
0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
2
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
Determines if the FTM counter is reinitialized when the selected trigger for the synchronization is
detected. The REINIT bit configures the synchronization when SYNCMODE is zero.
0 FTM counter continues to count normally.
1 FTM counter is updated with its initial value when the selected trigger is detected.
1
CNTMAX
Maximum Loading Point Enable
Selects the maximum loading point to PWM synchronization. See Boundary cycle and loading points. If
CNTMAX is one, the selected loading point is when the FTM counter reaches its maximum value (MOD
register).
0 The maximum loading point is disabled.
1 The maximum loading point is enabled.
0
CNTMIN
Minimum Loading Point Enable
Selects the minimum loading point to PWM synchronization. See Boundary cycle and loading points. If
CNTMIN is one, the selected loading point is when the FTM counter reaches its minimum value (CNTIN
register).
0 The minimum loading point is disabled.
1 The minimum loading point is enabled.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
710 Freescale Semiconductor, Inc.