Information

Table 3-13. Wakeup sources for LLWU inputs
Input Wakeup source Input Wakeup source
LLWU_P0 PTE1/LLWU_P0 pin LLWU_P12 PTD0/LLWU_P12 pin
LLWU_P1 PTE2/LLWU_P1 pin LLWU_P13 PTD2/LLWU_P13 pin
LLWU_P2 PTE4/LLWU_P2 pin LLWU_P14 PTD4/LLWU_P14 pin
LLWU_P3 PTA4/LLWU_P3 pin
1
LLWU_P15 PTD6/LLWU_P15 pin
LLWU_P4 PTA13/LLWU_P4 pin LLWU_M0IF LPTMR
2
LLWU_P5 PTB0/LLWU_P5 pin LLWU_M1IF CMP0
2
LLWU_P6 PTC1/LLWU_P6 pin LLWU_M2IF CMP1
2
LLWU_P7 PTC3/LLWU_P7 pin LLWU_M3IF Reserved
LLWU_P8 PTC4/LLWU_P8 pin LLWU_M4IF TSI
2
LLWU_P9 PTC5/LLWU_P9 pin LLWU_M5IF RTC Alarm
2
LLWU_P10 PTC6/LLWU_P10 pin LLWU_M6IF Reserved
LLWU_P11 PTC11/LLWU_P11 pin LLWU_M7IF RTC Seconds
2
1. The EZP_CS signal is checked only on Chip Reset not VLLS, so a VLLS wakeup via a non-reset source does not cause
EzPort mode entry. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit
from the low power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag
as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
3.3.5 MCM Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Miscellaneous
Control Module
(MCM)
Transfers
ARM Cortex-M4
core
PPB
Figure 3-9. MCM configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description Miscellaneous control
module (MCM)
MCM
System memory map System memory map
Clocking Clock distribution
Power management Power management
Table continues on the next page...
System modules
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
72 Freescale Semiconductor, Inc.