Information

FTMx_DEADTIME field descriptions (continued)
Field Description
When DTVAL is 2, 2 counts are inserted.
This pattern continues up to a possible 63 counts.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
35.3.16 FTM External Trigger (FTMx_EXTTRIG)
This register:
• Indicates when a channel trigger was generated
• Enables the generation of a trigger when the FTM counter is equal to its initial
• Selects which channels are used in the generation of the channel triggers
Several channels can be selected to generate multiple triggers in one PWM period.
Channels 6 and 7 are not used to generate channel triggers.
Addresses: FTM0_EXTTRIG is 4003_8000h base + 6Ch offset = 4003_806Ch
FTM1_EXTTRIG is 4003_9000h base + 6Ch offset = 4003_906Ch
Bit 31 30 29 28 27 26 25 24
R
Reserved[0:16]
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
Reserved[15:0]
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
Reserved[7:0]
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
TRIGF
INITTRIGEN
CH1TRIG CH0TRIG CH5TRIG CH4TRIG CH3TRIG CH2TRIG
W
Reset
0 0 0 0 0 0 0 0
FTMx_EXTTRIG field descriptions
Field Description
31–8
Reserved
This field is reserved.
7
TRIGF
Channel Trigger Flag
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
720 Freescale Semiconductor, Inc.