Information

FTMx_FMS field descriptions (continued)
Field Description
0
FAULTF0
Fault Detection Flag 0
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF0 by reading the FMS register while FAULTF0 is set and then writing a 0 to FAULTF0 while
there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF0 has no
effect. FAULTF0 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF0 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
35.3.19 Input Capture Filter Control (FTMx_FILTER)
This register selects the filter value for the inputs of channels.
Channels 4, 5, 6 and 7 do not have an input filter.
NOTE
Writing to the FILTER register has immediate effect and must
be done only when the channels 0, 1, 2, and 3 are not in input
modes. Failure to do this could result in a missing valid signal.
Addresses: FTM0_FILTER is 4003_8000h base + 78h offset = 4003_8078h
FTM1_FILTER is 4003_9000h base + 78h offset = 4003_9078h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved CH3FVAL CH2FVAL CH1FVAL CH0FVAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FILTER field descriptions
Field Description
31–16
Reserved
This field is reserved.
15–12
CH3FVAL
Channel 3 Input Filter
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
11–8
CH2FVAL
Channel 2 Input Filter
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
726 Freescale Semiconductor, Inc.