Information

FTMx_FLTCTRL field descriptions (continued)
Field Description
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input is disabled.
1 Fault input is enabled.
0
FAULT0EN
Fault Input 0 Enable
Enables the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input is disabled.
1 Fault input is enabled.
35.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)
This register has the control and status bits for the Quadrature Decoder mode.
Addresses: FTM0_QDCTRL is 4003_8000h base + 80h offset = 4003_8080h
FTM1_QDCTRL is 4003_9000h base + 80h offset = 4003_9080h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
PHAFLTREN PHBFLTREN
PHAPOL PHBPOL
QUADMODE
QUADIR TOFDIR
QUADEN
W
Reset
0 0 0 0 0 0 0 0
FTMx_QDCTRL field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
PHAFLTREN
Phase A Input Filter Enable
Table continues on the next page...
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 729