Information

FTMx_QDCTRL field descriptions (continued)
Field Description
Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is
defined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero.
0 Phase A input filter is disabled.
1 Phase A input filter is enabled.
6
PHBFLTREN
Phase B Input Filter Enable
Enables the filter for the quadrature decoder phase B input. The filter value for the phase B input is
defined by the CH1FVAL field of FILTER. The phase B filter is also disabled when CH1FVAL is zero.
0 Phase B input filter is disabled.
1 Phase B input filter is enabled.
5
PHAPOL
Phase A Input Polarity
Selects the polarity for the quadrature decoder phase A input.
0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of
this signal.
1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this
signal.
4
PHBPOL
Phase B Input Polarity
Selects the polarity for the quadrature decoder phase B input.
0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of
this signal.
1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this
signal.
3
QUADMODE
Quadrature Decoder Mode
Selects the encoding mode used in the Quadrature Decoder mode.
0 Phase A and phase B encoding mode.
1 Count and direction encoding mode.
2
QUADIR
FTM Counter Direction In Quadrature Decoder Mode
Indicates the counting direction.
0 Counting direction is decreasing (FTM counter decrement).
1 Counting direction is increasing (FTM counter increment).
1
TOFDIR
Timer Overflow Direction In Quadrature Decoder Mode
Indicates if the TOF bit was set on the top or the bottom of counting.
0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter
changes from its minimum value (CNTIN register) to its maximum value (MOD register).
1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter
changes from its maximum value (MOD register) to its minimum value (CNTIN register).
0
QUADEN
Quadrature Decoder Mode Enable
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
730 Freescale Semiconductor, Inc.