Information

FTMx_QDCTRL field descriptions (continued)
Field Description
Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM
counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 35-7.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Quadrature Decoder mode is disabled.
1 Quadrature Decoder mode is enabled.
35.3.22 Configuration (FTMx_CONF)
This register selects the number of times that the FTM counter overflow should occur
before the TOF bit to be set, the FTM behavior in BDM modes, the use of an external
global time base, and the global time base signal generation.
Addresses: FTM0_CONF is 4003_8000h base + 84h offset = 4003_8084h
FTM1_CONF is 4003_9000h base + 84h offset = 4003_9084h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
GTBEOUT GTBEEN
0
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
BDMMODE
0
NUMTOF
W
Reset
0 0 0 0 0 0 0 0
FTMx_CONF field descriptions
Field Description
31–11
Reserved
This read-only field is reserved and always has the value zero.
10
GTBEOUT
Global Time Base Output
Enables the global time base signal generation to other FTMs.
Table continues on the next page...
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 731