Information

FTMx_FLTPOL field descriptions (continued)
Field Description
0 The fault input polarity is active high. A one at the fault input indicates a fault.
1 The fault input polarity is active low. A zero at the fault input indicates a fault.
0
FLT0POL
Fault Input 0 Polarity
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A one at the fault input indicates a fault.
1 The fault input polarity is active low. A zero at the fault input indicates a fault.
35.3.24 Synchronization Configuration (FTMx_SYNCONF)
This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2,
when the hardware trigger j is detected.
Addresses: FTM0_SYNCONF is 4003_8000h base + 8Ch offset = 4003_808Ch
FTM1_SYNCONF is 4003_9000h base + 8Ch offset = 4003_908Ch
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
HWSOC HWINVC HWOM HWWRBUF
HWRSTCNT
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
SWSOC SWINVC SWOM SWWRBUF SWRSTCNT
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
SYNCMODE
0
SWOC INVC
0
CNTINC
0
HWTRIGMODE
W
Reset
0 0 0 0 0 0 0 0
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
734 Freescale Semiconductor, Inc.