Information

Addresses: FTM0_SWOCTRL is 4003_8000h base + 94h offset = 4003_8094h
FTM1_SWOCTRL is 4003_9000h base + 94h offset = 4003_9094h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
CH7OCV CH6OCV CH5OCV CH4OCV CH3OCV CH2OCV CH1OCV CH0OCV
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
CH7OC CH6OC CH5OC CH4OC CH3OC CH2OC CH1OC CH0OC
W
Reset
0 0 0 0 0 0 0 0
FTMx_SWOCTRL field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15
CH7OCV
Channel 7 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
14
CH6OCV
Channel 6 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
13
CH5OCV
Channel 5 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
12
CH4OCV
Channel 4 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
11
CH3OCV
Channel 3 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
10
CH2OCV
Channel 2 Software Output Control Value
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
738 Freescale Semiconductor, Inc.