Information

Table 3-15. Reference links to related information
Topic Related module Reference
Full description Crossbar switch Crossbar Switch
System memory map System memory map
Clocking Clock Distribution
Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core
Crossbar switch master DMA controller DMA controller
Crossbar switch master EzPort EzPort
Crossbar switch master USB FS/LS USB FS/LS
Crossbar switch slave Flash Flash
Crossbar switch slaves SRAM controllers SRAM configuration
Crossbar switch slave Peripheral bridges Peripheral bridge
Crossbar switch slave GPIO controller GPIO controller
3.3.6.1 Crossbar-Light Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core code bus 0
ARM core system bus 1
DMA/EzPort 2
USB OTG 3
NOTE
The DMA and EzPort share a master port. Since these modules
never operate at the same time, no configuration or arbitration
explanations are necessary.
3.3.6.2 Crossbar-Light Switch Slave Assignments
The slaves connected to the crossbar switch are assigned as follows:
Slave module Slave port number Protected by MPU?
Flash memory controller 0 No
SRAM controllers 1,2 No
Peripheral bridge 0/GPIO
1
3 No. Protection built into bridge.
1. See System memory map for access restrictions.
System modules
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
74 Freescale Semiconductor, Inc.