Information

Note
The Input Capture mode must be used only with CNTIN =
0x0000.
35.4.4.1 Filter for Input Capture mode
The filter function is only available on channels 0, 1, 2, and 3.
First, the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block. See the following figure.
system clock
5-bit up counter Logic to define
the filter output
filter output
divided by 4
channel (n) input after
the synchronizer
Logic to control
the filter counter
CHnFVAL[3:0]
C
S
Q
CLK
Figure 35-135. Channel input filter
When there is a state change in the input signal, the 5-bit counter is reset and starts
counting up. As long as the new state is stable on the input, the counter continues to
increment. If the 5-bit counter overflows, that is, the counter exceeds the value of
CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as
a pulse edge to the edge detector.
If the opposite edge appears on the input signal before it can be validated, the counter is
reset. At the next input transition, the counter starts counting again. Any pulse that is
shorter than the minimum value selected by CHnFVAL[3:0] (× 4 system clocks) is
regarded as a glitch and is not passed on to the edge detector. A timing diagram of the
input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then the
input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system clocks)
plus a further 4 rising edges of the system clock: two rising edges to the synchronizer,
one rising edge to the filter output, plus one more to the edge detector. In other words,
CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on
the channel input.
The clock for the 5-bit counter in the channel input filter is the system clock divided by 4.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
750 Freescale Semiconductor, Inc.