Information

TOF bit
...
...
0
1 1 1
2
2
3 3
4 45 5
0 0
previous value
previous value
channel (n) output
counter
overflow
counter
overflow
counter
overflow
channel (n)
match
channel (n)
match
CNT
MOD = 0x0005
CnV = 0x0003
CHnF bit
Figure 35-138. Example of the Output Compare mode when the match clears the
channel output
channel (n) output
CHnF bit
TOF bit
CNT
MOD = 0x0005
CnV = 0x0003
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
counter
overflow
...
0
1
2
3 4 5
0
1
2
3
4
5
0
1
...
previous value
previous value
Figure 35-139. Example of the Output Compare mode when the match sets the channel
output
Using the Output Compare mode is possible with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnV register, the CHnF bit is set and the
channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not
modified and controlled by FTM.
Note
The Output Compare mode must be used only with CNTIN =
0x0000.
35.4.6 Edge-Aligned PWM (EPWM) mode
The Edge-Aligned mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSnB = 1
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
752 Freescale Semiconductor, Inc.