Information

The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
pulse width
counter overflow
FTM counter =
MOD
period
2 x (CnV - CNTIN)
2 x (MOD - CNTINCNTIN)
FTM counter = CNTIN
channel (n) match
(FTM counting
is down)
channel (n) match
(FTM counting
is up)
counter overflow
FTM counter =
MOD
channel (n) output
Figure 35-143. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the FTM counter reaches the value in the CnV register,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up. See the following figure.
TOF bit
...
7
8 8
7 7 7
6 6 6
5 5 54 43 3
2 21
0
1
...
previous value
CNT
channel (n) output
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
channel (n) match in
down counting
counter
overflow
CHnF bit
MOD = 0x0008
CnV = 0x0005
Figure 35-144. CPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced high at the channel (n)
match when counting up. See the following figure.
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 755