Information

FTM counter
channel (n+1) match
channel (n+1) output
with COMP = 1
channel (n+1) output
with COMP = 0
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) match
Figure 35-162. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = 1:0)
FTM counter
channel (n+1) match
channel (n+1) output
with COMP = 1
channel (n+1) output
with COMP = 0
channel (n) output
with ELSnB:ELSnA = X:1
channel (n) match
Figure 35-163. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1)
35.4.10 Registers updated from write buffers
35.4.10.1 CNTIN register update
The following table describes when CNTIN register is updated:
Table 35-183. CNTIN register update
When Then CNTIN register is updated
CLKS[1:0] = 0:0 When CNTIN register is written, independent of FTMEN bit.
• FTMEN = 0, or
• CNTINC = 0
At the next system clock after CNTIN was written.
• FTMEN = 1,
• SYNCMODE = 1, and
• CNTINC = 1
By the CNTIN register synchronization.
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 765