Information

SWSYNC bit
system clock
software trigger event
write 1 to SWSYNC bit
selected loading point
PWM synchronization
SWSYNC bit
system clock
software trigger event
write 1 to SWSYNC bit
PWM synchronization
Figure 35-165. Software trigger event
35.4.11.3 Boundary cycle and loading points
The boundary cycle definition is important for the loading points for the registers MOD,
CNTIN, and C(n)V.
In Up counting mode, the boundary cycle is defined as when the counter wraps to its
initial value (CNTIN). If in Up-down counting mode, then the boundary cycle is defined
as when the counter turns from down to up counting and when from up to down counting.
The following figure shows the boundary cycles and the loading points for the registers.
In the Up Counting mode, the loading points are enabled if one of CNTMIN or CTMAX
bits are 1. In the Up-Down Counting mode, the loading points are selected by CNTMIN
and CNTMAX bits, as indicated in the figure. These loading points are safe places for
register updates thus allowing a smooth transitions in PWM waveform generation.
For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary
cycles are not used as loading points for registers updates. See the register
synchronization descriptions in the following sections for details.
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 769