Information

CPWMS = 0
0x00
00 01
0x01 0x02
0x03
0x04
0x05
initialization trigger
CLKS[1:0] bits
FTM counter
system clock
CNTIN = 0x0000
MOD = 0x000F
Figure 35-201. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and
a value different from zero is written to CLKS[1:0] bits
The initialization trigger output provides a trigger signal that is used for on-chip modules.
Note
The initialization trigger must be used only in Combine mode.
35.4.22 Capture Test mode
The Capture Test mode allows to test the CnV registers, the FTM counter and the
interconnection logic between the FTM counter and CnV registers.
In this test mode, all channels must be configured for Input Capture mode and FTM
counter must be configured to the Up counting.
When the Capture Test mode is enabled (CAPTEST = 1), the FTM counter is frozen and
any write to CNT register updates directly the FTM counter; see the following figure.
After it was written, all CnV registers are updated with the written value to CNT register
and CHnF bits are set. Therefore, the FTM counter is updated with its next value
according to its configuration. Its next value depends on CNTIN, MOD, and the written
value to FTM counter.
The next reads of CnV registers return the written value to the FTM counter and the next
reads of CNT register return FTM counter next value.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
798 Freescale Semiconductor, Inc.