Information

NOTE
FTM counter clock
write to MODE
CAPTEST bit
FTM counter
write to CNT
CHnF bit
CnV
- FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and
(MOD = 0xFFFF)
- FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0)
0x0300
0x78AC
set CAPTEST
clear CAPTEST
write 0x78AC
0x1056
0x1053
0x1055
0x1054
0x78AC
0x78AD
0x78AE0x78AF
0x78B0
Figure 35-202. Capture Test mode
35.4.23 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits. See
the following table.
Table 35-191. Channel DMA transfer request
DMA CHnIE Channel DMA Transfer Request Channel Interrupt
0 0 The channel DMA transfer request is not
generated.
The channel interrupt is not generated.
0 1 The channel DMA transfer request is not
generated.
The channel interrupt is generated if (CHnF = 1).
1 0 The channel DMA transfer request is not
generated.
The channel interrupt is not generated.
1 1 The channel DMA transfer request is generated
if (CHnF = 1).
The channel interrupt is not generated.
If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading
CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit. See
the following table.
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 799