Information

Section Number Title Page
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................177
9.1.1 References....................................................................................................................................................179
9.2 The Debug Port.............................................................................................................................................................179
9.2.1 JTAG-to-SWD change sequence.................................................................................................................180
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................180
9.3 Debug Port Pin Descriptions.........................................................................................................................................181
9.4 System TAP connection................................................................................................................................................181
9.4.1 IR Codes.......................................................................................................................................................181
9.5 JTAG status and control registers.................................................................................................................................182
9.5.1 MDM-AP Control Register..........................................................................................................................183
9.5.2 MDM-AP Status Register............................................................................................................................185
9.6 Debug Resets................................................................................................................................................................187
9.7 AHB-AP........................................................................................................................................................................187
9.8 ITM...............................................................................................................................................................................188
9.9 Core Trace Connectivity...............................................................................................................................................188
9.10 TPIU..............................................................................................................................................................................188
9.11 DWT.............................................................................................................................................................................188
9.12 Debug in Low Power Modes........................................................................................................................................189
9.12.1 Debug Module State in Low Power Modes.................................................................................................190
9.13 Debug & Security.........................................................................................................................................................190
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................191
10.2 Signal Multiplexing Integration....................................................................................................................................191
10.2.1 Port control and interrupt module features..................................................................................................192
10.2.2 PCRn reset values for port A.......................................................................................................................192
10.2.3 Clock gating.................................................................................................................................................192
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
8 Freescale Semiconductor, Inc.