Information

3.3.10.3 EWM_OUT pin state in low power modes
During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance
state. A user has the option to control the logic state of the pin using an external pull
device or by configuring the internal pull device. When the CPU enters a Run mode from
Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop
mode. When the CPU enters Run mode from Power Down, the pin returns to its reset
state.
3.3.11 Watchdog Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
WDOG
Mode Controller
Peripheral
bridge 0
Register
access
Figure 3-15. Watchdog configuration
Table 3-23. Reference links to related information
Topic Related module Reference
Full description Watchdog Watchdog
System memory map System memory map
Clocking Clock distribution
Power management Power management
Mode Controller (MC) System Mode Controller
3.3.11.1 WDOG clocks
This table shows the WDOG module clocks and the corresponding chip clocks.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 81