Information

Table 35-193. FTM behavior when the chip Is in BDM mode (continued)
BDMMODE
FTM
Counter
CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers
11 Functional
mode
can be set Functional mode Functional mode
Note that if BDMMODE[1:0] = 2’b00 then the channels outputs remain at the value
when the chip enters in BDM mode, because the FTM counter is stopped. However, the
following situations modify the channels outputs in this BDM mode.
• Write any value to CNT register; see Counter reset. In this case, the FTM counter is
updated with the CNTIN register value and the channels outputs are updated to the
initial value – except for those channels set to Output Compare mode.
• FTM counter is reset by PWM Synchronization mode; see FTM counter
synchronization) In this case, the FTM counter is updated with the CNTIN register
value and the channels outputs are updated to the initial value – except for channels
in Output Compare mode.
• In the channels outputs initialization, the channel (n) output is forced to the CH(n)OI
bit value when the value 1 is written to INIT bit. See Initialization.
Note
The BDMMODE[1:0] = 2’b00 must not be used with the Fault
control. Even if the fault control is enabled and a fault condition
exists, the channels outputs values are as defined above.
35.4.27 Intermediate load
The PWMLOAD register allows software to update the MOD, CNTIN, and C(n)V
registers with the content of the register buffer at a defined load point. In this case, it is
not required to use the PWM synchronization control.
There are multiple possible loading points for intermediate load:
Table 35-194. When possible loading points are enabled
Loading point Enabled
When the FTM counter wraps from MOD value to CNTIN
value
Always
At the channel (j) match (FTM counter = C(j)V) When CHjSEL = 1
The following figure shows some examples of enabled loading points.
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 813