Information

Timer n
Timer 1
PIT
Peripheral
load_value
PIT
Triggers
bus clock
bus
Peripheral
Iinterrupts
registers
Figure 36-1. Block diagram of the PIT
NOTE
See the chip configuration details for the number of PIT
channels used in this MCU.
36.1.2 Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
• Ability of timers to generate interrupts
• Maskable interrupts
• Independent timeout periods for each timer
36.2 Signal description
The PIT module has no external pins.
Signal description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
820 Freescale Semiconductor, Inc.