Information

PIT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_7138 Timer Control Register (PIT_TCTRL3) 32 R/W 0000_0000h
36.3.4/
824
4003_713C Timer Flag Register (PIT_TFLG3) 32 R/W 0000_0000h
36.3.5/
824
36.3.1 PIT Module Control Register (PIT_MCR)
This register enables or disables the PIT timer clocks and controls the timers when the
PIT enters the Debug mode.
Address: PIT_MCR is 4003_7000h base + 0h offset = 4003_7000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MDIS
FRZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
PIT_MCR field descriptions
Field Description
31–2
Reserved
This read-only field is reserved and always has the value zero.
1
MDIS
Module Disable
Disables the module clock. This field must be enabled before any other setup is done.
0 Clock for PIT timers is enabled.
1 Clock for PIT timers is disabled.
0
FRZ
Freeze
Allows the timers to be stopped when the device enters the Debug mode.
0 Timers continue to run in Debug mode.
1 Timers are stopped in Debug mode.
Memory map/register description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
822 Freescale Semiconductor, Inc.