Information

36.3.2 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Addresses: LDVAL0 is 4003_7000h base + 100h offset = 4003_7100h
LDVAL1 is 4003_7000h base + 110h offset = 4003_7110h
LDVAL2 is 4003_7000h base + 120h offset = 4003_7120h
LDVAL3 is 4003_7000h base + 130h offset = 4003_7130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TSV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_LDVALn field descriptions
Field Description
31–0
TSV
Timer Start Value
Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt
and load this register value again. Writing a new value to this register will not restart the timer; instead the
value will be loaded after the timer expires. To abort the current cycle and start a timer period with the
new value, the timer must be disabled and enabled again.
36.3.3 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Addresses: CVAL0 is 4003_7000h base + 104h offset = 4003_7104h
CVAL1 is 4003_7000h base + 114h offset = 4003_7114h
CVAL2 is 4003_7000h base + 124h offset = 4003_7124h
CVAL3 is 4003_7000h base + 134h offset = 4003_7134h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TVL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_CVALn field descriptions
Field Description
31–0
TVL
Current Timer Value
Represents the current timer value, if the timer is enabled.
NOTE: • If the timer is disabled, do not use this field as its value is unreliable.
• The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is
set.
Chapter 36 Periodic Interrupt Timer (PIT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 823