Information

36.3.4 Timer Control Register (PIT_TCTRLn)
These registers contain the control bits for each timer.
Addresses: TCTRL0 is 4003_7000h base + 108h offset = 4003_7108h
TCTRL1 is 4003_7000h base + 118h offset = 4003_7118h
TCTRL2 is 4003_7000h base + 128h offset = 4003_7128h
TCTRL3 is 4003_7000h base + 138h offset = 4003_7138h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIE
TEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TCTRLn field descriptions
Field Description
31–2
Reserved
This read-only field is reserved and always has the value zero.
1
TIE
Timer Interrupt Enable
When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an
interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first.
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
0
TEN
Timer Enable
Enables or disables the timer.
0 Timer n is disabled.
1 Timer n is enabled.
36.3.5 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Addresses: TFLG0 is 4003_7000h base + 10Ch offset = 4003_710Ch
TFLG1 is 4003_7000h base + 11Ch offset = 4003_711Ch
TFLG2 is 4003_7000h base + 12Ch offset = 4003_712Ch
TFLG3 is 4003_7000h base + 13Ch offset = 4003_713Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIF
W w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
824 Freescale Semiconductor, Inc.