Information

LPTMRx_CSR field descriptions (continued)
Field Description
0 The value of CNR is not equal to CMR and increments.
1 The value of CNR is equal to CMR and increments.
6
TIE
Timer Interrupt Enable
When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
0 Timer interrupt disabled.
1 Timer interrupt enabled.
5–4
TPS
Timer Pin Select
Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the
LPTMR is disabled. The input connections vary by device. See the chip configuration details for
information on the connections to these inputs.
00 Pulse counter input 0 is selected.
01 Pulse counter input 1 is selected.
10 Pulse counter input 2 is selected.
11 Pulse counter input 3 is selected.
3
TPP
Timer Pin Polarity
Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the
LPTMR is disabled.
0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
2
TFC
Timer Free-Running Counter
When clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR
to reset on overflow. TFC must be altered only when the LPTMR is disabled.
0 CNR is reset whenever TCF is set.
1 CNR is reset on overflow.
1
TMS
Timer Mode Select
Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled.
0 Time Counter mode.
1 Pulse Counter mode.
0
TEN
Timer Enable
When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the
LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered.
0 LPTMR is disabled and internal logic is reset.
1 LPTMR is enabled.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
832 Freescale Semiconductor, Inc.