Information

38.6.6 CMT Modulator Status and Control Register (CMT_MSC)
This register contains the modulator and carrier generator enable (MCGEN), end of cycle
interrupt enable (EOCIE), FSK mode select (FSK), baseband enable (BASE), extended
space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status bit.
Address: CMT_MSC is 4006_2000h base + 5h offset = 4006_2005h
Bit 7 6 5 4
Read
EOCF
CMTDIV
EXSPC
Write
Reset
0 0 0 0
Bit
3 2 1 0
Read
BASE FSK EOCIE MCGEN
Write
Reset
0 0 0 0
CMT_MSC field descriptions
Field Description
7
EOCF
End Of Cycle Status Flag
Sets when:
• The modulator is not currently active and MCGEN is set to begin the initial CMT
transmission.
• At the end of each modulation cycle while MCGEN is set. This is recognized
when a match occurs between the contents of the space period register and
the down counter. At this time, the counter is initialized with, possibly new
contents of the mark period buffer, CMD1 and CMD2, and the space period
register is loaded with, possibly new contents of the space period buffer, CMD3
and CMD4.
This flag is cleared by reading MSC followed by an access of CMD2 or CMD4, or by
the DMA transfer.
0 End of modulation cycle has not occured since the flag last cleared.
1
End of modulator cycle has occurred.
6–5
CMTDIV
CMT Clock Divide Prescaler
Causes the CMT to be clocked at the IF signal frequency, or the IF frequency divided
by 2 ,4, or 8 . This field must not be changed during a transmission because it is not
double-buffered.
00 IF ÷ 1
01 IF ÷ 2
10 IF ÷ 4
11 IF ÷ 8
Table continues on the next page...
Chapter 38 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 849