Information

38.6.11 CMT Primary Prescaler Register (CMT_PPS)
This register is used to set the Primary Prescaler Divider field (PPSDIV).
Address: CMT_PPS is 4006_2000h base + Ah offset = 4006_200Ah
Bit 7 6 5 4 3 2 1 0
Read 0
PPSDIV
Write
Reset
0 0 0 0 0 0 0 0
CMT_PPS field descriptions
Field Description
7–4
Reserved
This read-only field is reserved and always has the value zero.
3–0
PPSDIV
Primary Prescaler Divider
Divides the CMT clock to generate the Intermediate Frequency clock enable to the secondary prescaler.
0000 Bus clock ÷ 1
0001
Bus clock ÷ 2
0010
Bus clock ÷ 3
0011
Bus clock ÷ 4
0100
Bus clock ÷ 5
0101
Bus clock ÷ 6
0110
Bus clock ÷ 7
0111
Bus clock ÷ 8
1000
Bus clock ÷ 9
1001
Bus clock ÷ 10
1010
Bus clock ÷ 11
1011
Bus clock ÷ 12
1100
Bus clock ÷ 13
1101
Bus clock ÷ 14
1110
Bus clock ÷ 15
1111
Bus clock ÷ 16
Chapter 38 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 853