Information

38.6.12 CMT Direct Memory Access Register (CMT_DMA)
This register is used to enable/disable direct memory access (DMA).
Address: CMT_DMA is 4006_2000h base + Bh offset = 4006_200Bh
Bit 7 6 5 4 3 2 1 0
Read 0
DMA
Write
Reset
0 0 0 0 0 0 0 0
CMT_DMA field descriptions
Field Description
7–1
Reserved
This read-only field is reserved and always has the value zero.
0
DMA
DMA Enable
Enables the DMA protocol.
0 DMA transfer request and done are disabled.
1
DMA transfer request and done are enabled.
38.7 Functional description
The CMT module primarily consists of clock divider, carrier generator, and modulator.
38.7.1 Clock divider
The CMT was originally designed to be based on an 8 MHz bus clock that could be
divided by 1, 2, 4, or 8 according to the specification. To be compatible with higher bus
frequency, the primary prescaler (PPS) was developed to receive a higher frequency and
generate a clock enable signal called intermediate frequency (IF). This IF must be
approximately equal to 8 MHz and will work as a clock enable to the secondary
prescaler. The following figure shows the clock divider block diagram.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
854 Freescale Semiconductor, Inc.