Information

For low-frequency signals with large periods, high-resolution duty cycles as a percentage
of the total period, are possible.
The carrier signal is generated by counting a register-selected number of input clocks
(125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The
period is determined by the total number of clocks counted. The duty cycle is determined
by the ratio of high-time clocks to total clocks counted. The high and low time values are
user-programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the
generation of dual-frequency FSK protocols without CPU intervention.
Note
Only nonzero data values are allowed. The carrier generator
will not work if any of the count values are equal to zero.
MSC[MCGEN] must be set and MSC[BASE] must be cleared to enable carrier generator
clocks. When MSC[BASE] is set, the carrier output to the modulator is held high
continuously. The following figure represents the block diagram of the clock generator.
Clock and output control
= ?
Secondary High Count Register
Primary High Count Register
8-bit up counter
CLK
CLR
CMTCLK
BASE
FSK
MCGEN
CARRIER OUT (f
cg
)
Secondary Low Count Register
Primary Low Count Register
Primary/
Secondary
Select
= ?
Figure 38-15. Carrier generator block diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of
the counter are compared with the appropriate high or low count value register. When the
compare value is reached, the counter is reset to a value of 0x01, and the compare is
redirected to the other count value register.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
856 Freescale Semiconductor, Inc.