Information

Assuming that the high time count compare register is currently active, a valid compare
will cause the carrier output to be driven low. The counter will continue to increment
starting at the reset value of 0x01. When the value stored in the selected low count value
register is reached, the counter will again be reset and the carrier output will be driven
high.
The cycle repeats, automatically generating a periodic signal which is directed to the
modulator. The lower frequency with maximum period, f
max
, and highest frequency with
minimum period, f
min
, which can be generated, are defined as:
f
max
= f
CMTCLK
÷ (2 * 1) Hz
f
min
= f
CMTCLK
÷ (2 * (2
8
− 1)) Hz
In the general case, the carrier generator output frequency is:
f
cg
= f
CMTCLK
÷ (High count + Low count) Hz
Where: 0 < High count < 256 and
0 < Low count < 256
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low
+ high time. As the input clock period is fixed, the duty cycle resolution will be
proportional to the number of counts required to generate the desired carrier period.
38.7.3 Modulator
The modulator block controls the state of the infrared out signal (IRO). The modulator
output is gated on to the IRO signal when the modulator/carrier generator is enabled. .
When the modulator/carrier generator is disabled, the IRO signal is controlled by the state
of the IRO latch. OC[CMTPOL] enables the IRO signal to be active-high or active-low.
The following table describes the functions of the modulators in different modes:
Table 38-20. Mode functions
Mode Function
Time The modulator can gate the carrier onto the modulator
output.
Baseband The modulator can control the logic level of the modulator
output.
Table continues on the next page...
Chapter 38 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 857