Information

MS bit
16 bits
Mode
Load
FSK
BASE
EXSPC
EOCIE
16 bits
1 6
=?
Counter
Primary/Secondary select
0
1 6
17-bit down counter *
CMTCMD1:CMTCMD2
Clock control
Carrier out (fcg)
Modulator
out
Modulator gate
EOC Flag set
Module interrupt request
System control
CMTCLK
Space period register
CMTCMD3:CMTCMD4
* Denotes hidden register
8
Figure 38-16. Modulator block diagram
38.7.3.1 Time mode
When the modulator operates in Time mode, or, when MSC[MCGEN] is set, and
MSC[BASE] and MSC[FSK] are cleared:
• The modulation mark period consists of an integer number of (CMTCLK ÷ 8) clock
periods.
• The modulation space period consists of 0 or an integer number of (CMTCLK ÷ 8)
clock periods.
With an 8 MHz IF and MSC[CMTDIV] = 00, the modulator resolution is 1 μs and has a
maximum mark and space period of about 65.535 ms each . See Figure 38-17 for an
example of the Time and Baseband mode outputs.
The mark and space time equations for Time and Baseband mode are:
t
mark
= (CMD1:CMD2 + 1) ÷ (f
CMTCLK
÷ 8)
t
space
= CMD3:CMD4 ÷ (f
CMTCLK
÷ 8)
where CMD1:CMD2 and CMD3:CMD4 are the decimal values of the concatenated
registers.
Chapter 38 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 859