Information

Write accesses to any register by non-supervisor mode software, when the supervisor
access bit in the control register is clear, will terminate with a bus error.
Read accesses by non-supervisor mode software complete as normal.
Writing to a register protected by the write access register or lock register does not
generate a bus error, but the write will not complete.
Reading a register protected by the read access register does not generate a bus error, but
the register will read zero.
RTC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_D000 RTC Time Seconds Register (RTC_TSR) 32 R/W 0000_0000h
39.2.1/
867
4003_D004 RTC Time Prescaler Register (RTC_TPR) 32 R/W 0000_0000h
39.2.2/
868
4003_D008 RTC Time Alarm Register (RTC_TAR) 32 R/W 0000_0000h
39.2.3/
868
4003_D00C RTC Time Compensation Register (RTC_TCR) 32 R/W 0000_0000h
39.2.4/
869
4003_D010 RTC Control Register (RTC_CR) 32 R/W 0000_0000h
39.2.5/
870
4003_D014 RTC Status Register (RTC_SR) 32 R/W 0000_0001h
39.2.6/
871
4003_D018 RTC Lock Register (RTC_LR) 32 R/W 0000_00FFh
39.2.7/
872
4003_D01C RTC Interrupt Enable Register (RTC_IER) 32 R/W 0000_0007h
39.2.8/
874
4003_D800 RTC Write Access Register (RTC_WAR) 32 R/W 0000_00FFh
39.2.9/
875
4003_D804 RTC Read Access Register (RTC_RAR) 32 R/W 0000_00FFh
39.2.10/
876
39.2.1 RTC Time Seconds Register (RTC_TSR)
Address: RTC_TSR is 4003_D000h base + 0h offset = 4003_D000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TSR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 39 Real Time Clock (RTC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 867