Information

Program flash
Flash configuration field
FlexNVM base address
Program flash base address
Flash memory base address
Registers
FlexNVM
FlexRAM
FlexRAM base address
Figure 3-20. Flash memory map
3.5.1.4 Flash Security
How flash security is implemented on this device is described in Chip Security.
3.5.1.5 Flash Modes
The flash memory operates in NVM normal and NVM special modes. The flash memory
enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset), or
the system is under debug mode. Otherwise, flash memory operates in NVM normal
mode.
3.5.1.6 Erase All Flash Contents
In addition to software, the entire flash memory may be erased external to the flash
memory in two ways:
1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for
more details.
2. Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set
to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared
when the mass erase completes.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 87