Information

RTC_CR field descriptions (continued)
Field Description
0 The 32kHz clock is output to other peripherals
1 The 32kHz clock is not output to other peripherals
8
OSCE
Oscillator Enable
0 32.768 kHz oscillator is disabled.
1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling
the time counter to allow the 32.768 kHz clock time to stabilize.
7–4
Reserved
This read-only field is reserved and always has the value zero.
3
UM
Update Mode
Allows the SR[TCE] to be written even when the Status Register is locked. When set, the SR[TCE] can
always be written if the SR[TIF] or SR[TOF] are set or if the SR[TCE] is clear.
0 Registers cannot be written when locked.
1 Registers can be written when locked under limited conditions.
2
SUP
Supervisor Access
0 Non-supervisor mode write accesses are not supported and generate a bus error.
1 Non-supervisor mode write accesses are supported.
1
WPE
Wakeup Pin Enable
The wakeup pin is optional and not available on all devices.
0 Wakeup pin is disabled.
1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts and the chip is powered
down.
0
SWR
Software Reset
0 No effect
1 Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers. The
SWR bit is cleared after VBAT POR and by software explicitly clearing it.
39.2.6 RTC Status Register (RTC_SR)
Address: RTC_SR is 4003_D000h base + 14h offset = 4003_D014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TCE
0 TAF TOF TIF
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Chapter 39 Real Time Clock (RTC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 871