Information

USBx_ISTAT field descriptions (continued)
Field Description
4
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 milliseconds. The sleep
timer is reset by activity on the USB bus.
3
TOKDNE
This bit is set when the current token being processed has completed. The processor should immediately
read the STAT register to determine the EndPoint and BD used for this token. Clearing this bit (by writing
a one) causes the STAT register to be cleared or the STAT holding register to be loaded into the STAT
register.
2
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
In Host mode this bit is set when the SOF threshold is reached, so that software can prepare for the next
SOF.
1
ERROR
This bit is set when any of the error conditions within the ERRSTAT register occur. The processor must
then read the ERRSTAT register to determine the source of the error.
0
USBRST
This bit is set when the USB Module has decoded a valid USB reset. This informs the Microprocessor that
it should write 0x00 into the address register and enable endpoint 0. USBRST is set after a USB reset has
been detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been
removed and then reasserted.
40.4.10 Interrupt Enable Register (USBx_INTEN)
The Interrupt Enable Register contains enable bits for each of the interrupt sources within
the USB Module. Setting any of these bits enables the respective interrupt source in the
ISTAT register. This register contains the value of 0x00 after a reset.
Addresses: USB0_INTEN is 4007_2000h base + 84h offset = 4007_2084h
Bit 7 6 5 4 3 2 1 0
Read
STALLEN
ATTACHEN RESUMEEN
SLEEPEN
TOKDNEEN SOFTOKEN
ERROREN USBRSTEN
Write
Reset
0 0 0 0 0 0 0 0
USBx_INTEN field descriptions
Field Description
7
STALLEN
STALL Interrupt Enable
0 The STALL interrupt is not enabled.
1 The STALL interrupt is enabled.
6
ATTACHEN
ATTACH Interrupt Enable
0 The ATTACH interrupt is not enabled.
1 The ATTACH interrupt is enabled.
5
RESUMEEN
RESUME Interrupt Enable
0 The RESUME interrupt is not enabled.
1 The RESUME interrupt is enabled.
Table continues on the next page...
Memory map/Register definitions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
902 Freescale Semiconductor, Inc.