Information

USBx_INTEN field descriptions (continued)
Field Description
4
SLEEPEN
SLEEP Interrupt Enable
0 The SLEEP interrupt is not enabled.
1 The SLEEP interrupt is enabled.
3
TOKDNEEN
TOKDNE Interrupt Enable
0 The TOKDNE interrupt is not enabled.
1 The TOKDNE interrupt is enabled.
2
SOFTOKEN
SOFTOK Interrupt Enable
0 The SOFTOK interrupt is not enabled.
1 The SOFTOK interrupt is enabled.
1
ERROREN
ERROR Interrupt Enable
0 The ERROR interrupt is not enabled.
1 The ERROR interrupt is enabled.
0
USBRSTEN
USBRST Interrupt Enable
0 The USBRST interrupt is not enabled.
1 The USBRST interrupt is enabled.
40.4.11 Error Interrupt Status Register (USBx_ERRSTAT)
The Error Interrupt Status Register contains enable bits for each of the error sources
within the USB Module. Each of these bits are qualified with their respective error enable
bits. All bits of this Register are logically OR'd together and the result placed in the
ERROR bit of the ISTAT register. After an interrupt bit has been set it may only be
cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error
conditions is detected. Therefore, the interrupt does not typically correspond with the end
of a token being processed. This register contains the value of 0x00 after a reset.
Addresses: USB0_ERRSTAT is 4007_2000h base + 88h offset = 4007_2088h
Bit 7 6 5 4 3 2 1 0
Read BTSERR 0 DMAERR BTOERR DFN8 CRC16 CRC5EOF PIDERR
Write w1c w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0
USBx_ERRSTAT field descriptions
Field Description
7
BTSERR
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the
error.
Table continues on the next page...
Chapter 40 Universal Serial Bus OTG Controller (USBOTG)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 903