Information

In VLLS1 and VLLS0 no SRAM is retained; however, the 32-byte register file is
available.
3.5.4 System Register File Configuration
This section summarizes how the module has been configured in the chip.
Register file
Peripheral
bridge 0
Register
access
Figure 3-24. System Register file configuration
Table 3-32. Reference links to related information
Topic Related module Reference
Full description Register file Register file
System memory map System memory map
Clocking Clock distribution
Power management Power management
3.5.4.1 System Register file
This device includes a 32-byte register file that is powered in all power modes.
Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.
3.5.5 VBAT Register File Configuration
This section summarizes how the module has been configured in the chip.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 91