Information

USBDCD memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_5014 TIMER1 register (USBDCD_TIMER1) 32 R/W 000A_0028h
41.4.5/
935
4003_5018 TIMER2 register (USBDCD_TIMER2) 32 R/W 0028_0001h
41.4.6/
936
41.4.1 Control register (USBDCD_CONTROL)
Contains the control and interrupt bit fields.
Address: USBDCD_CONTROL is 4003_5000h base + 0h offset = 4003_5000h
Bit 31 30 29 28 27 26 25 24
R
0 0 0
W
SR START
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
IE
W
Reset
0 0 0 0 0 0 0 1
Bit
15 14 13 12 11 10 9 8
R
Reserved
IF
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
0 0
W
IACK
Reset
0 0 0 0 0 0 0 0
USBDCD_CONTROL field descriptions
Field Description
31–26
Reserved
This read-only field is reserved and always has the value zero.
25
SR
Software Reset
Determines whether a software reset is performed.
0 Do not perform a software reset.
1 Perform a software reset.
24
START
Start Change Detection Sequence
Determines whether the charger detection sequence is initiated.
Table continues on the next page...
Memory map/Register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
930 Freescale Semiconductor, Inc.