Information

Table 3-36. Reference links to related information (continued)
Topic Related module Reference
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.1.1 ADC instantiation information
This device contains one ADC.
3.7.1.1.1 Number of ADC channels
The number of ADC channels present on the device is determined by the pinout of the
specific device package. For details regarding the number of ADC channel available on a
particular package, refer to the signal multiplexing chapter of this MCU.
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC (4K samples/sec) that may
have considerable load on the CPU. Though using PDB to trigger ADC may reduce some
CPU load, The ADC supports DMA request functionality for higher performance when
the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can
trigger the DMA (via DMA req) on conversion completion.
Connections/Channel Assignment
3.7.1.3.1 ADC0 Connections/Channel Assignment
NOTE
As indicated by the following sections, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
3.7.1.3
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 95