Information

• Programmable transfer attributes on a per-frame basis:
• 2 transfer attribute registers
• Serial clock (SCK) with programmable polarity and phase
• Various programmable delays
• Programmable serial frame size of 4–16 bits, expandable by software control
• SPI frames longer than 16 bits can be supported using the continuous
selection format
• Continuously held chip select capability
• 5 peripheral chip selects (PCSs), expandable to 32 with external demultiplexer
• Deglitching support for up to 16 PCS with external demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
• TX FIFO is not full (TFFF)
• RX FIFO is not empty (RFDF)
• Interrupt conditions:
• End of Queue reached (EOQF)
• TX FIFO is not full (TFFF)
• Transfer of current frame complete (TCF)
• Attempt to transmit with an empty Transmit FIFO (TFUF)
• RX FIFO is not empty (RFDF)
• Frame received while Receive FIFO is full (RFOF)
• Global interrupt request line
• Modified SPI transfer formats for communication with slower peripheral devices
• Power-saving architectural features:
• Support for Stop mode
• Support for Doze mode
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 959