Information

43.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3
PCS1 – PCS3 are output signals in Master mode.
In Slave mode, these signals are unused.
43.2.3 PCS4 — Peripheral Chip Select 4
In Master mode, PCS4 is an output signal.
In Slave mode, this signal is unused.
43.2.4 SIN — Serial Input
SIN is a serial data input signal.
43.2.5 SOUT — Serial Output
SOUT is a serial data output signal.
43.2.6 SCK — Serial Clock
SCK is a serial communication clock signal. In Master mode, the DSPI generates the
SCK. In Slave mode, SCK is an input from an external bus master.
43.3 Memory Map/Register Definition
Register accesses to memory addresses that are reserved or undefined result in a transfer
error. Write access to the POPR also results in a transfer error.
SPI memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C000 DSPI Module Configuration Register (SPI0_MCR) 32 R/W 0000_4001h
43.3.1/
965
Table continues on the next page...
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 963