Information

SPI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C008 DSPI Transfer Count Register (SPI0_TCR) 32 R/W 0000_0000h
43.3.2/
968
4002_C00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR0)
32 R/W 7800_0000h
43.3.3/
968
4002_C00C
DSPI Clock and Transfer Attributes Register (In Slave
Mode) (SPI0_CTAR0_SLAVE)
32 R/W 7800_0000h
43.3.4/
973
4002_C010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR1)
32 R/W 7800_0000h
43.3.3/
968
4002_C02C DSPI Status Register (SPI0_SR) 32 R/W 0201_0000h
43.3.5/
974
4002_C030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI0_RSER)
32 R/W 0000_0000h
43.3.6/
977
4002_C034
DSPI PUSH TX FIFO Register In Master Mode
(SPI0_PUSHR)
32 R/W 0000_0000h
43.3.7/
979
4002_C034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI0_PUSHR_SLAVE)
32 R/W 0000_0000h
43.3.8/
981
4002_C038 DSPI POP RX FIFO Register (SPI0_POPR) 32 R 0000_0000h
43.3.9/
981
4002_C03C DSPI Transmit FIFO Registers (SPI0_TXFR0) 32 R 0000_0000h
43.3.10/
982
4002_C040 DSPI Transmit FIFO Registers (SPI0_TXFR1) 32 R 0000_0000h
43.3.10/
982
4002_C044 DSPI Transmit FIFO Registers (SPI0_TXFR2) 32 R 0000_0000h
43.3.10/
982
4002_C048 DSPI Transmit FIFO Registers (SPI0_TXFR3) 32 R 0000_0000h
43.3.10/
982
4002_C07C DSPI Receive FIFO Registers (SPI0_RXFR0) 32 R 0000_0000h
43.3.11/
983
4002_C080 DSPI Receive FIFO Registers (SPI0_RXFR1) 32 R 0000_0000h
43.3.11/
983
4002_C084 DSPI Receive FIFO Registers (SPI0_RXFR2) 32 R 0000_0000h
43.3.11/
983
4002_C088 DSPI Receive FIFO Registers (SPI0_RXFR3) 32 R 0000_0000h
43.3.11/
983
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
964 Freescale Semiconductor, Inc.