Information

43.3.1 DSPI Module Configuration Register (SPIx_MCR)
Contains bits to configure various attributes associated with DSPI operations. The HALT
and MDIS bits can be changed at any time, but the effect takes place only on the next
frame boundary. Only the HALT and MDIS bits in the MCR can be changed, while the
DSPI is in the Running state.
Addresses: SPI0_MCR is 4002_C000h base + 0h offset = 4002_C000h
Bit 31 30 29 28 27 26 25 24
R
MSTR
CONT_SCKE
DCONF FRZ MTFE Reserved ROOE
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
Reserved PCSIS[4:0]
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
DOZE MDIS DIS_TXF DIS_RXF
0 0
SMPL_PT
W
CLR_TXF CLR_RXF
Reset
0 1 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
0 0 0
HALT
W
Reset
0 0 0 0 0 0 0 1
SPIx_MCR field descriptions
Field Description
31
MSTR
Master/Slave Mode Select
Configures the DSPI for either Master mode or Slave mode.
0 DSPI is in Slave mode.
1 DSPI is in Master mode.
30
CONT_SCKE
Continuous SCK Enable
Enables the Serial Communication Clock (SCK) to run continuously.
0 Continuous SCK disabled.
1 Continuous SCK enabled.
29–28
DCONF
DSPI Configuration
Selects among the different configurations of the DSPI.
00 SPI
01 Reserved
Table continues on the next page...
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 965