Information

SPIx_MCR field descriptions (continued)
Field Description
10 Reserved
11 Reserved
27
FRZ
Freeze
Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug
mode.
0 Do not halt serial transfers in Debug mode.
1 Halt serial transfers in Debug mode.
26
MTFE
Modified Timing Format Enable
Enables a modified transfer format to be used.
0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
25
Reserved
This field is reserved.
24
ROOE
Receive FIFO Overflow Overwrite Enable
In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwrite
existing data. If the RX FIFO is full and new data is received, the data from the transfer, generating the
overflow, is ignored or shifted into the shift register.
0 Incoming data is ignored.
1 Incoming data is shifted into the shift register.
23–21
Reserved
This field is reserved.
20–16
PCSIS[4:0]
Peripheral Chip Select x Inactive State
Determines the inactive state of PCSx.
0 The inactive state of PCSx is low.
1 The inactive state of PCSx is high.
15
DOZE
Doze Enable
Provides support for an externally controlled Doze mode power-saving mechanism.
0 Doze mode has no effect on DSPI.
1 Doze mode disables DSPI.
14
MDIS
Module Disable
Allows the clock to be stopped to the non-memory mapped logic in the DSPI effectively putting the DSPI
in a software-controlled power-saving state. The reset value of the MDIS bit is parameterized, with a
default reset value of 0.
0 Enables DSPI clocks.
1 Allows external logic to disable DSPI clocks.
13
DIS_TXF
Disable Transmit FIFO
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
966 Freescale Semiconductor, Inc.