Information

SPIx_CTARn_SLAVE field descriptions (continued)
Field Description
22
Reserved
This read-only field is reserved and always has the value zero.
21–0
Reserved
This read-only field is reserved and always has the value zero.
43.3.5 DSPI Status Register (SPIx_SR)
SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear flag
bits in the SR by writing a 1 to them. Writing a 0 to a flag bit has no effect. This register
may not be writable in Module Disable mode due to the use of power saving
mechanisms.
Addresses: SPI0_SR is 4002_C000h base + 2Ch offset = 4002_C02Ch
Bit 31 30 29 28 27 26 25 24
R
TCF TXRXS 0 EOQF TFUF 0 TFFF 0
W
w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 1 0
Bit
23 22 21 20 19 18 17 16
R
0 0 0 0 RFOF 0 RFDF 0
W
w1c w1c
Reset
0 0 0 0 0 0 0 1
Bit
15 14 13 12 11 10 9 8
R
TXCTR TXNXTPTR
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
RXCTR POPNXTPTR
W
Reset
0 0 0 0 0 0 0 0
SPIx_SR field descriptions
Field Description
31
TCF
Transfer Complete Flag
Indicates that all bits in a frame have been shifted out. TCF remains set until it is cleared by writing a 1 to
it.
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
974 Freescale Semiconductor, Inc.