Information

For operation of triggers in different modes, refer to Power Management chapter.
3.7.1.7 Alternate clock
For this device, the alternate clock is connected to OSCERCLK.
NOTE
This clock option is only usable when OSCERCLK is in the
MHz range. A system with OSCERCLK in the kHz range has
the optional clock source below minimum ADC clock operating
frequency.
3.7.1.8 ADC low-power modes
This table shows the ADC low-power modes and the corresponding chip low-power
modes.
Table 3-37. ADC low-power modes
Module mode Chip mode
Wait Wait, VLPW
Normal Stop Stop, VLPS
Low Power Stop LLS, VLLS3, VLLS2, VLLS1, VLLS0
3.7.2 CMP Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Connections/Channel Assignment
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
98 Freescale Semiconductor, Inc.