Information

43.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)
RXFRn provide visibility into the RX FIFO for debugging purposes. Each register is an
entry in the RX FIFO. The RXFRs are read-only. Reading the RXFRx registers does not
alter the state of the RX FIFO.
Addresses: SPI0_RXFR0 is 4002_C000h base + 7Ch offset = 4002_C07Ch
SPI0_RXFR1 is 4002_C000h base + 80h offset = 4002_C080h
SPI0_RXFR2 is 4002_C000h base + 84h offset = 4002_C084h
SPI0_RXFR3 is 4002_C000h base + 88h offset = 4002_C088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_RXFRn field descriptions
Field Description
31–0
RXDATA
Receive Data
Contains the received SPI data.
43.4 Functional description
The Serial Peripheral Interface (DSPI) block supports full-duplex, synchronous serial
communications between MCUs and peripheral devices. All communications are done
with SPI-like protocol.
The DSPI has the following configurations:
• SPI Configuration in which the DSPI operates as a basic SPI or a queued SPI.
The DCONF field in the DSPI Module Configuration Register (MCR) determines the
DSPI Configuration. See ../dil/DSPI_BG_V5x.xml#MCR for the DSPI configuration
values.
The CTARn registers hold clock and transfer attributes. The SPI configuration allows to
select which CTAR to use on a frame by frame basis by setting a field in the SPI
command.
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 983