Information

See ../dil/DSPI_BG_V5x.xml#CTAR_MASTER_2 for information on the fields of
CTAR registers.
Typical master to slave connections are shown in the following figure. When a data
transfer operation is performed, data is serially shifted a predetermined number of bit
positions. Because the modules are linked, data is exchanged between the master and the
slave. The data that was in the master shift register is now in the shift register of the
slave, and vice versa. At the end of a transfer, the TCF bit in the SR is set to indicate a
completed transfer.
Shift Register
Baud Rate
Generator
Shift Register
SOUT
SCK
PCSx
DSPI Slave
DSPI Master
SIN
SOUT
SIN
SS
SCK
Figure 43-47. SPI serial protocol overview
Generally, more than one slave device can be connected to the DSPI master. 6 Peripheral
Chip Select (PCS) signals of the DSPI masters can be used to select which of the slaves
to communicate with. Refer to the chip configuration chapter for the number of PCS
signals used in this MCU.
The three DSPI configurations share transfer protocol and timing properties which are
described independently of the configuration in Transfer formats . The transfer rate and
delay settings are described in DSPI baud rate and clock delay generation.
43.4.1 Start and Stop of DSPI transfers
The DSPI has two operating states: Stopped and Running. Both the states are independent
of DSPI configuration. The default state of the DSPI is Stopped. In the Stopped state, no
serial transfers are initiated in Master mode and no transfers are responded to in Slave
mode. The Stopped state is also a safe state for writing the various configuration registers
of the DSPI without causing undetermined results. In the Running state serial transfers
take place.
The TXRXS bit in the SR indicates the state of DSPI. The bit is set if the module is in
Running state.
The DSPI starts or transitions to Running when all of the following conditions are true:
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
984 Freescale Semiconductor, Inc.