Information
• SR[EOQF] bit is clear
• MCU is not in the Debug mode or the MCR[FRZ] bit is clear
• MCR[HALT] bit is clear
The DSPI stops or transitions from Running to Stopped after the current frame when any
one of the following conditions exist:
• SR[EOQF] bit is set
• MCU in the Debug mode and the MCR[FRZ] bit is set
• MCR[HALT] bit is set
State transitions from Running to Stopped occur on the next frame boundary if a transfer
is in progress, or immediately if no transfers are in progress.
43.4.2 Serial Peripheral Interface (SPI) configuration
The SPI configuration transfers data serially using a shift register and a selection of
programmable transfer attributes. The DSPI is in SPI configuration when the DCONF
field in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMA
controller transfers the SPI data from the external to DSPI RAM queues to a TX FIFO
buffer. The received data is stored in entries in the RX FIFO buffer. The host CPU or the
DMA controller transfers the received data from the RX FIFO to memory external to the
DSPI. The operation of FIFO buffers is described in Transmit First In First Out (TX
FIFO) buffering mechanism, Transmit First In First Out (TX FIFO) buffering mechanism
and Receive First In First Out (RX FIFO) buffering mechanism. The interrupt and DMA
request conditions are described in Interrupts/DMA requests.
The SPI configuration supports two block-specific modes—Master mode and Slave
mode. In Master mode the DSPI initiates and controls the transfer according to the fields
of the executing SPI Command. In Slave mode, the DSPI responds only to transfers
initiated by a bus master external to the DSPI and the SPI command field space is
reserved.
43.4.2.1 Master mode
In SPI Master, mode the DSPI initiates the serial transfers by controlling the SCK and the
PCS signals. The executing SPI Command determines which CTARs will be used to set
the transfer attributes and which PCS signals to assert . The command field also contains
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 985