Information

The TX FIFO Counter field (TXCTR) in the DSPI Status Register (SR) indicates the
number of valid entries in the TX FIFO. The TXCTR is updated every time a 8- or 16-bit
write takes place to the Data Field of DSPI_PUSHR or SPI data is transferred into the
shift register from the TX FIFO.
The TXNXTPTR field indicates the TX FIFO Entry that will be transmitted during the
next transfer. The TXNXTPTR field is incremented every time SPI data is transferred
from the TX FIFO to the shift register. The maximum value of the field is equal to the
maximum implemented TXFR number and it rolls over after reaching the maximum.
43.4.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by
writing to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in
the SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controller
indicates that a write to PUSHR is complete. Writing a '1' to the TFFF bit also clears it.
The TFFF can generate a DMA request or an interrupt request. See Transmit FIFO Fill
Interrupt or DMA Request for details.
The DSPI ignores attempts to push data to a full TX FIFO, and the state of the TX FIFO
does not change and no error condition is indicated.
43.4.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift
register. Entries are transferred from the TX FIFO to the shift register and shifted out as
long as there are valid entries in the TX FIFO. Every time an entry is transferred from the
TX FIFO to the shift register, the TX FIFO Counter decrements by one. At the end of a
transfer, the TCF bit in the SR is set to indicate the completion of a transfer. The TX
FIFO is flushed by writing a '1' to the CLR_TXF bit in MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TX
FIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. See
Transmit FIFO Underflow Interrupt Request for details.
43.4.2.5 Receive First In First Out (RX FIFO) buffering mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds
4 received SPI data frames. The number of entries in the RX FIFO is device-specific. SPI
data is added to the RX FIFO at the completion of a transfer when the received data in the
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 987